Microelectronic circuits have been fabricated on semiconductors by various processes for many years. As circuits have become more complex, various techniques have developed to permit the efficient design and verification of circuits and systems. One important technique in microelectronic circuit design is the use of standard cells or “splines,” which are pre-configured circuit units that are designed to perform common functions correctly and efficiently, and to be useable in a variety of contexts. For example, a spline might implement a single-bit memory cell, and be designed so that a multi-bit register of arbitrary width can be added to a circuit simply by placing an appropriate number of copies of the spline next to each other. The spline might usefully have power and ground lines arranged so that the entire register could be powered simply by providing power to fixed locations on one of the spline copies; input and output lines could similarly be placed so that the register could easily be connected to surrounding circuitry without requiring extensive, complex routing.
Individual splines can be extensively modeled, verified, and optimized, so that arrays of splines may approach the space-efficiency of a full-custom layout to perform the same function, with greatly improved confidence in the correctness and manufacturability of the resulting part. In addition, a correction or improvement in a spline will automatically benefit any circuit that uses the spline, and if the spline's connection points are undisturbed, very little additional work may be required to produce devices using the improved layout.
Splines are often designed to be placed in regular arrays, where each copy is located at a fixed displacement from the previous copy. Sometimes, the displacement is simply a translation of a particular distance along a single axis, as shown in FIG. 1, 110; but some splines might be suitable for use in two-dimensional arrays (120), for placement after translation and rotation (130), placement after reflection (140), or after combinations of translation, reflection, and rotation (150).
Most microelectronic circuits include input and output (“I/O”) facilities to exchange data with other circuits and components in a system. Such facilities often operate in parallel: a number of data signals are transmitted or received simultaneously over several physical signal lines, rather than being sent or received sequentially over a single line. Thus, a standard circuit to produce or detect data signals can frequently be reused, and may be a good candidate for implementation in a spline.
In many situations, physically and/or logically proximate lines carry signals in both directions; sometimes a single physical interconnection will carry an outbound (transmitted) signal from a circuit, and shortly thereafter carry an inbound (received) signal to the circuit. In these cases, a spline containing both a transmitter and a receiver may be a useful building block for a circuit designer. The transmitters and receivers themselves may perform either single-ended or differential signaling, methods which are well-known in the art.
Since the transmitter and receiver circuits frequently communicate with system components outside the microelectronic circuit (as opposed to intra-circuit communications), they are often placed at or near the perimeter of a circuit layout, and connect directly to conductors leading to pins or contact points on the exterior of an integrated circuit package. These conductors are usually spaced at regular intervals, so transmitter and/or receiver splines must be sized and designed so that their contact points match the conductor positions. The external connection-point constraints of a microelectronics package substrate and the orientation of the package pins is called the package's “ball-out,” while the orientation of the contact points of a spline is called the spline's “bump-out.”
A common practice is to include a single transmitter and a single receiver within one spline. Grouping a transmitter together with a receiver in a spline facilitates the scalability of the I/O design interface, because additional splines can be added as needed to produce the number of transmitter and receiver pairs required by a given interface. FIG. 2 shows a single spline containing a transmitter 210 and a receiver 220. Power 230 and ground 240 lines are provided so that copies of the spline replicated along the spline's short dimension can easily obtain power from (or through) their neighbors, as shown in inset 250. The transmitter portion of the spline connects to external circuitry through a connection point 260, while the receiver portion is connected through connection 270. The location of these connection points (the spline's bump-out) may be constrained by the physical arrangement of a carrier or lead frame that connects points on the semiconductor substrate with external electrodes or pins, as defined by the ball-out. Note that the array of spline copies in inset 250 has the transmitter and receiver connection points arranged in a regular “zig-zag” pattern 255 to optimize density and distribution of the contact points. At other locations within the spline (e.g. 280 and 290), connection points between the spline circuitry and other circuits within the microelectronic device are provided. The locations of these latter connection points may not be limited by external physical constraints, but it may nevertheless be undesirable to change these locations if a new or improved spline is to be substituted, because changing the locations may necessitate alteration of the interconnect from the spline to other internal circuits. The task of redesigning internal interconnects of circuits that are already highly optimized and extensively validated and tested may turn out to be more expensive and involved than any benefits realized from an improved spline.